Stands for “Complex Instruction Set Computing.” This is a type of microprocessor design. The CISC architecture contains a large set of computer instructions that range from very simple to very complex and specialized.
A reduced instruction set computer, or RISC, is a computer instruction set that allows a computer’s microprocessor to have fewer cycles per instruction than a complex instruction set computer. A RISC computer has a small set of simple and general instructions, rather than a large set of complex and specialized ones.
Read: Differentiate Between 2 Tier and 3 Tier Architecture
| CISC | RISC |
| In CISC computer architecture there is a large set of instructions available. A large set of instruction variable formats (16-64 bits/inst) | In RISC architecture small set of instruction with fixed (32 bit) format and most register-based instruction |
| There is CISC architecture lots of addressing modes are available so we can do lots of operation using different addressing modes. | There in RICS architecture least number of addressing modes so we can perform the least number of operation |
| 12-24 addressing modes are available in CISC. | 3-5 addressing modes are available in RISC. |
| General-purpose register and cache design 8-24 GPRs, mostly with a unified cache | General-purpose register and cache design 32-192 GPRs, with split cache(data and instruction) |
| Clock rate and CPI 33-50 MHzCPI 2-15 | Clock rate and CPI 50-150MHzCPI <1.5 |
| It is based on Micro programmed control unit | It is based on Hardwired control unit |